The present invention relates to methods of forming a semiconductor structure, and particularly to methods of stacking semiconductor substrates while maximally compensating for bowing of the semiconductor substrates and a bonded assembly of a plurality of substrates thereby formed.
3D integration, or chip stacking, refers to a method of assembling two or more semiconductor chips so that the semiconductor chips that are placed in physical proximity to one another are also electrically connected among one another. 3D integration is typically performed vertically, i.e., one chip is placed above or below another chip. When two chips are brought together vertically, a set of conductive contact structures on the top surface of an underlying chip is aligned to another set of conductive contact structures on the bottom surface of an overlying chip. The conductive structures may be formed on the side of metal interconnect structures, or they may be formed on the side of a substrate on which semiconductor devices are formed.
Multiple semiconductor substrates can be vertically stacked in 3D integration. Currently, wafer-level 3D integration is demonstrated for 2-4 layer process in which each layer includes a single semiconductor substrate. Limiting factors in the increase in the number of layers in a three-dimensional integration ODD stack include bowing of the substrates at wafer bonding and non-uniformity of thickness within each substrate.
Specifically, there is a maximum bowing that can be accommodated during bonding of two substrates. If a holding wafer has intrinsic bow of I, and if the incremental wafer bow B is added after a top wafer is bonded and trimmed to the holding wafer, then a bonded structure that includes the holding wafer and 2N number of additional bonded wafers has a total wafer bow of 2N×B+I. Available instrumentation for bonding 300 mm wafers can handle wafers bow in the range from +300 microns (bowl-shaped bowing) to −100 microns (dome-shaped bowing). Typically, a wafer bow of a single wafer after front-end-of-line (FEOL) processes that form semiconductor devices and back-end-of-line (BEOL) processes that form metal interconnect structures ranges from +300 microns to −100 microns depending on technology. Thus, bonding even three wafers can be a challenge with current 3D integration technology.
While it is possible in theory to minimize the bow introduced by top wafer processing in FEOL and BEOL processing steps and bonding process steps, for example, by employing film compensation techniques, such processes are costly and time consuming. In practice, the change of wafer bow due to FEOL and BEOL processing steps and the bonding process steps is unavoidable due to process limitations. Because the total bow of bonded structures is cumulative, even a small change of wafer bow can result in a significant wafer bow when multiple wafers stacked. The wafer bow limits the maximum number of layer 3DI structures that can be stacked.